106 points · 46 comments · 4 days ago · CorRupT9
github.comkey features: Custom 16-instruction Harvard ISA, 8-bit fixed format, 4 general purpose registers
Hardwired control unit built entirely from AND/OR gate logic matrix
Dual-phase clocking to eliminate race conditions
Bootstrap Control Unit that cold-boots via ROM-to-RAM transfer Early-exit conditional branching that saves upto 25% cycles when conditions aren't met
Full design specification document with version control
Since this was our first time doing such teamwork and a new thing we used RISC based system that fetches an 8-bit instruction from Instruction memory 4 bits of which translate to an instruction the last two bits are for source and destination registers. There are a total of 4 registers in the system with two memory units namely Data SRAM and I SRAM, the system follows a Harvard architecture.
There are design discrepancies too since it was our first time designing such a system and on top of that completely hardwired too.
To solve the problem of cold booting a bootloader is present too that copies the contents of a temporary ROM into instruction RAM and then hands over the reins to the CPU.
We also implemented conditional branching as well as early exit branching too that only checks for zero or carry flag and branches without wasting cycles, if the conditions are not met the Program counter increments.
Moreover we also created a complete documentation with version control describing each necessary part assuming prior knowledge.
Please take a look at it at https://github.com/c0rRupT9/STEPLA-1
For future development I want to implement a RISC CPU using FPGA's and connect it to an actual DRAM. We are also selling the full spec document and Logisim files for $5 to fund our passion https://tcfdiq.gumroad.com/l/zyyux Thankyou!
dreamcompiler
gabrielsroka
osigurdson
loloquwowndueo
Back in the day i built a 4-bit CPU on a breadboard (it was huge actually spanned 3 breadboards). Programming the ROM by hand like cavemen (to be fair it was the cave ages). We didn’t carry cameras in our pockets so sadly we didn’t get a picture.
pjc50
It doesn't appear to have any kind of interrupts, which is quite a limitation for actual usecases, but also makes the architecture much simpler.
The use of dual phase clocking is interesting. The document describes it as having the control and data paths operating on opposite phases. I'm curious as to where you got this technique from, since it's not common (apart from the use of both edges by DDR RAM). I also suspect that it would go away if you had better tooling for managing setup and hold violations (does logisim do that for you, or did you have to manage it manually somehow?). Not all FPGA tools like nonstandard clock architectures.
peterus
gsliepen
jdw64
sarmadgulzar
throwaway2016a
daniban
momoraul
alfienightshift
chrisakoury
Very implressive tbh
You should include a screenshot of the logisim diagram
hahooh
bcjdjsndon
HerbManic
hypfer
Now do it the other way round and make the 8 bit cpus become a 2nd year EE student.
assimpleaspossi
>me and my friends ...
My friends and I...
Every output bit m of microcode can be equivalently expressed as a logic function of n inputs where the microcode has n incoming address lines. This no less transparent than pure logic if you know the contents of the microcode. Microcode is often preferred because changing it is much easier than changing a bunch of gate logic. IMHO factoring your design into registers vs. control signals and putting the control signals into microcode makes the design more transparent than having a giant sea of gates.